This invention is in the field of analog circuits. More specifically, embodiments are directed to the correction of mismatch in analog circuits realized in an integrated circuit device.
Metal-oxide semiconductor (MOS) technology has become an attractive vehicle for implementing analog circuits in recent years. For example, the continuing trend toward large-scale integration has extended to “mixed-signal” integrated circuits, motivating the use of a single technology for both the digital and the analog functions in the same device. MOS analog circuits, such as operational transconductance amplifiers (OTAs), can attain significantly improved bandwidths and reduced power consumption over their bipolar counterparts, especially when realized in complementary MOS (CMOS) technology.
FIG. 1 illustrates an example of a conventional MOS OTA. Current source 9, for example a p-channel MOS transistor with its source at the Vdd power supply voltage and its gate receiving a regulated voltage, applies tail current Itail to the sources of input p-channel MOS transistors M1, M2, which receive input voltages V1, V2, respectively, at their gates. Transistors M1 and M2 are each connected in series with diode-connected n-channel MOS transistors M3 and M5, respectively. The gate and drain of transistor M3 is connected to the gate of n-channel MOS transistor M4 in current mirror fashion, and the gate and drain of transistor M2 is likewise connected to the gate of n-channel MOS transistor M6 in the output leg. The source/drain path of transistor M4 is connected in series with diode-connected p-channel MOS transistor M7, which has its gate and drain connected in current mirror fashion with the gate of p-channel MOS transistor M8 in the output leg. As such, three current mirrors (M3 and M4; M5 and M6; and M7 and M8) are present in this conventional MOS OTA.
In operation, with all transistors in saturation, the differential input voltage V1-V2 determines the split of tail current Itail into currents I1, I2 conducted by transistors M1, M2, respectively. Current I1 conducted by transistor M3 is mirrored as current I4 through transistor M4, and similarly current I2 is mirrored as current I6 through transistor M6. Current I7 conducted by transistor M7 is equal to current I4, and thus current I1; this current is mirrored as current I8 through transistor M8. Accordingly, current I8 into terminal OUT is equal to current I1 through transistor M1, based on input voltage V1, while current I6 out of terminal OUT is equal to current I2 through transistor M2, which is based on input voltage V2. Output current IOUT from this OTA is thus the current difference I8-I6, which is defined by the differential input voltage V1-V2.
However, mismatch between MOS transistors raises a serious challenge in analog circuits, particularly in differential amplifiers and OTAs such as that of FIG. 1. As known in the art, mismatch between MOS transistors can result from differences in the layout and position of the transistors in the integrated circuit, and from random variations in wafer fabrication processes that affect individual transistors differently. If, for example, all transistors in the OTA of FIG. 1 are well-matched, a zero input differential voltage V1-V2 will result in a zero output current IOUT, since transistors M1, M2 will evenly split tail current Itail into equal currents I1 and I2. Mismatch between transistors M1 and M2, on the other hand, will cause an unequal split of tail current Itail at zero input differential voltage, and the resulting difference between currents I1 and I2 will be reflected by a non-zero output current IOUT. The primary effect of device mismatch in differential input OTAs is thus a non-zero input offset voltage, and corresponding error in the output current.
Conventional circuit techniques for reducing offset include auto-zeroing techniques, correlated double sampling, chopper stabilization, and the like. According to another approach, many analog integrated circuits can now be “trimmed”, for example to reduce the input offset voltage of the op amp. Trimming is typically performed at manufacture, after electrical measurement or other evaluation of the performance of the raw circuit as manufactured. Conventional digital trimming is accomplished by selectively opening one or more fuses (or closing antifuses), by laser trimming of resistors. Another conventional approach to trimming analog circuits is digital programming of floating gate metal-oxide-semiconductor (MOS) transistors, in which the state of the transistor is defined by charge trapped at a floating gate electrode. Programming of the device is accomplished through such mechanisms as Fowler-Nordheim tunneling and hot carrier injection. These floating gate transistors essentially function as an electrically-erasable programmable read-only memory (EEPROM) or “flash” memory in this digital trimming application.
By way of further background, various types of analog floating gate devices are known in the art. These analog floating gate devices are integrated circuit structures that include a transistor having a floating gate electrode that can be programmed (i.e., charged or discharged) to a precise analog voltage, rather than to either an on state or an off state to which floating gate transistors are typically programmed in digital memory such as EEPROMs or flash memory. Examples of the physical construction of analog floating gate devices are described in U.S. Pat. Nos. 8,593,846 and 8,779,550, and in U.S. Patent Application Publication No. US 2015/0364480, all commonly assigned herewith and incorporated herein by this reference.